Generally speaking, a DCFL logic circuit is a logic circuit constructed by connecting field effect transistors directly in series or in parallel. In this logic circuit, GaAs metal semiconductor FETs (hereinafter referred to as MESFET) or high electron mobility transistors (hereinafter referred to as HEMT) are employed as constituent transistors. This logic circuit is often driven by -2 V power supply. More particularly, when logic signals are input and output between a semiconductor integrated circuit and an external circuit, ECL (Emitter Coupled Logic) levels, in which H level V.sub.H is -0.9 V and L level V.sub.L is -1.7 V are employed as an input/output level of the logic signals. The semiconductor integrated circuit usually has a structure in which -2 V power supply for inputting and outputting at ECL level is supplied from the outside. Therefore, -2 V power supply itself is employed in the DCFL logic circuit included in the semiconductor integrated circuit.
A DCFL logic circuit operates sufficiently at a driving voltage of 1 V. For example, when the voltage of the -2 V power supply supplied from the outside of the semiconductor integrated circuit is divided inside the circuit into 1 V between power supply voltage V.sub.DD (0 V) and V.sub.MM (-1 V) and 1 V between power supply voltage V.sub.MM (-1 V) and V.sub.TT (-2 V), and the DCFL logic circuit is driven at the driving voltage of 1 V, power dissipation of the semiconductor integrated circuit is reduced by lowering the power supply voltage, and if a HEMT is employed in this logic circuit, an increase in delay time is also avoided.
However, when the voltage of -2 V power supply is divided into two parts, as described above, and predetermined logic circuits are driven respectively by power supply voltages V.sub.MM and V.sub.TT and by power supply voltages V.sub.DD and V.sub.MM, the input/output level of the logic circuit in the lower voltage side driven by power supply voltages V.sub.MM and V.sub.TT has H level V.sub.H of approximately -1.3 V and L level V.sub.L of approximately -1.9 V. On the other hand, the input/output level of the logic circuit in the higher voltage side driven by power supply voltages V.sub.DD and V.sub.MM has H level V.sub.H of approximately -0.3 V and L level V.sub.L of approximately -0.9 V. Therefore, the input/output levels are unfavorably different between the logic circuit in the higher voltage side and the logic circuit in the lower voltage side. Then, in the conventional semiconductor integrated circuit of DCFL logic circuit type, a logic circuit converting an input/output level (hereinafter also referred to as level converting circuit) is provided between the logic circuit in the lower voltage side and the logic circuit in the higher voltage side.
FIG. 9(a) is a diagram illustrating construction of a conventional DCFL logic circuit having a level converting circuit, and FIG. 9(b) is a diagram illustrating a specific circuit of the DCFL logic circuit. In the figures, a DCFL logic circuit 200 includes a lower voltage side inverter 1 driven by -2 V power supply V.sub.TT and -1 V power supply V.sub.MM, a higher voltage side inverter 3 driven by -1 V power supply V.sub.MM and 0 V power supply V.sub.DD, and a level converting inverter 2 which transmits an output from the lower voltage side inverter 1 into the higher voltage side inverter 3 for level conversion. Here, the circuits are designed so that a predetermined node in the logic circuit 200 becomes -1 V power supply, V.sub.MM, as a result of 0 V power supply V.sub.DD and -2 V power supply V.sub.TT supplied from outside.
As shown in FIG. 9(b), a load transistor Q4 and a switching transistor Q5 constituting the lower voltage side inverter 1 are connected in series between -2 V power supply V.sub.TT and -1 V power supply V.sub.MM. The gate of the transistor Q5 and the connecting node between the transistors Q4 and Q5 are, respectively, an input node IN and an output node N1 of the inverter 1.
A load transistor Q6 and a switching transistor Q7 constituting the higher voltage side inverter 3 are connected in series between 0 V power supply V.sub.DD and -1 V power supply V.sub.MM. The gate of the transistor Q7 and the connecting node between the transistors Q6 and Q7 are, respectively, an input node N2 and an output node OUT of the inverter 3.
A load transistor Q1 and a switching transistor Q2, the level converting inverter 2, are connected in series between 0 V power supply V.sub.DD and -2 V power supply V.sub.TT. The gate of the transistor Q2 and the connecting node between both transistors are, respectively, an input node N1 of the level converting inverter 2 (the output node of the inverter 1) and an output node N2 of the inverter 2 (the input node of the inverter 3). The source-to-drain resistance of the switching transistor Q2 in its on-state (hereinafter referred to as ON resistance) is approximately one-tenth of the source-to-drain resistance of the load transistor Q1.
Here, as described above, GaAs MESFETs or HEMTs are employed as the transistors Q1, Q2, Q4 to Q7. In these transistors, differently from a metal oxide semiconductor (MOS) transistor, a Schottky junction is present between the gate and source (drain), and the Schottky barrier voltage is around 0.7 V. Further, the transistors Q1, Q4 and Q6 are depletion type transistors, and the transistors Q2, Q5 and Q7 are enhancement type transistors.
FIG. 10(a) is a cross section illustrating a structure of a conventional GaAs MESFET. In the figure, a MESFET 5 has a structure in which a source electrode 6 and a drain electrode 8 are disposed on an n-type GaAs layer 5b that is disposed on a semi-insulating GaAs substrate 5a and a predetermined space is present between a gate electrode 7 and the source and drain electrodes 6 and 8. A Schottky junction is present between the gate electrode 7 and the n-type GaAs layer 5a.
FIG. 10(b) is a cross section illustrating a structure of a conventional HEMT transistor. In the figure, a HEMT 15 has a structure in which a non-doped GaAs layer 15b and a Si-doped AlGaAs layer 15c are successively disposed on a semi-insulating GaAs substrate 15a. A source electrode 16 and a drain electrode 18 are disposed on the AlGaAs layer 15c, and a gate electrode 17 is disposed between and spaced from the electrodes 16 and 18. As in the MESFET, a Schottky junction is present between the gate electrode 17 and the AlGaAs layer 15c.
Next, description is given of the operation.
When the input node IN of the inverter 1 is at H level V.sub.H (-1.3 V), L level V.sub.L (-1.9 V) is output to the output node N1. Then, the inverter 2 receives this L level V.sub.L and outputs H level V.sub.H (-0.3 V). After this H level V.sub.H is input to the inverter 3, the output node N3 is at L level V.sub.L (-0.9 V).
On the other hand, when the input node IN of the inverter 1 is at L level V.sub.L (-1.9 V), H level V.sub.H (-1.3 V) is output to the output node N1. Thereby, the level of output node N2 of the inverter 2 is inverted to L level V.sub.L (-1.8 V). After this L level V.sub.L is input to the inverter 3, the output node N3 of the inverter 3 is at H level V.sub.H (-0.3 V).
H level V.sub.H and L level V.sub.L of the output node of the inverter 2 in the above-described operations are respectively at around -0.3 V and -1.8 V as described below. More particularly, when L level V.sub.L (-1.9 V) is input to the input node N1 of the inverter 2, i.e., the gate of the transistor Q2, the transistor Q2 is off. Here, a current flowing through the transistor Q1 hardly flows between the drain and the source of the transistor Q2, and flows in a current path through the gate of the transistor Q7 from the drain of the transistor Q1 to the source of the transistor Q7. Therefore, H level at the inverter 2 output is at -0.3 V, which is higher than the source voltage of the transistor Q7 (-1 V), by the Schottky barrier voltage (approximately 0.7 V).
When H level V.sub.H (-1.3 V) is input to the transistor Q2, the transistor Q2 is turned on, resulting in a source-to-drain resistance which is around one-tenth of the source-to-drain resistance of the transistor Q1. Therefore, a voltage at output node N2 of the inverter 2 is a value obtained by dividing a differential voltage 2 V between 0 V power supply V.sub.DD and -2 V power supply V.sub.TT by the source-to-drain resistances of the transistors Q2 and Q1.
More particularly, supposing that the source-to-drain resistance of the load transistor Q1 is R.sub.1 (=10r), another ON resistance of the switching transistor Q2 is R.sub.2 (=r), the voltage V.sub.2 at the output node of the inverter 2 is represented as follows: ##EQU1## Therefore, L level at the inverter 2 output is approximately -1.8 V.
As described above, the output level of the level converting inverter 2 comprising the transistors Q1 and Q2 is at H level V.sub.H at around -0.3 V and at L level V.sub.L at around -1.8 V. As a result, the logic voltage swing is approximately 1.5 V.
However, since the DCFL logic circuit conventionally operates with the logic voltage swing of about 0.6 V, if the circuit operates with the logic voltage swing of about 1.5 V like the above-described level converting inverter 2, operating speed is unfavorably decreased. In other words, in the inverter 2, in inverting its output, electrical charges are stored in and drained from the gate of the transistor Q7 or the like, by the transistors Q1 and Q2. However, if this logic voltage swing of the inverter 2 increases, the times required to charge and discharge the gate of transistor Q7 are unfavorably increased in response to an increase in the logic voltage swing, whereby the inverter 2 does not operate at high speed.
FIG. 1 of Japanese Published Patent Application No. 63-90918 discloses a DCFL logic circuit in which a load element R1 and a switching FET 1 are connected in series between higher voltage power supply V.sub.DD and lower voltage power supply V.sub.SS. The gate of the FET serves as an input node and the connecting node between the FET and the load element serves as an output node. A load resistance R2 and an FET 2 are connected in series with each other and in parallel with the load element R1, and negative feedback control of the FET 2 is provided through the FET 3 by the output from the logic circuit to obtain both a high switching speed and operating margin, which are in a trade-off relation. In this logic circuit, however, since a switching element or a feedback path for signals is required to charge the resistance of the load element, the circuit construction for adjusting output level is complicated, unfavorably increasing the area occupied by the logic circuit on the substrate. In addition, in this logic circuit, L level is increased by lowering the resistance value of the load element 1, increasing the power dissipation of the circuit.